MMIC (monolithic microwave integrated circuit) voltage controlled analog phase shifter

ABSTRACT

The invention relates to a voltage controlled analog phase shifter for operation at millimeter and microwave wavelengths using MMIC (Monolithic Microwave Integrated circuit) fabrication techniques. The phase shifter is formed of an artificial transmission line consisting of multiple unit elements in which each unit element contains a serial transmission line-inductance and a shunt diode capacitance which is variable as a function of an applied potential. In the design, the interconnecting transmission lines may be a small fraction of a wavelength, substantially less than one-quarter wavelength, and of high impedance relative to the characteristic impedance of the phase shifter. In consequence of the lumped design, each unit element, and a phase shifter using a plurality of such unit elements may be very small. The design also exhibits a low to negligible power consumption.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to integrated circuits for use at microwave andmillimeter wave frequencies, and more particularly to voltage controlledanalog phase shifters of MMIC design

2. Prior Art

There is a need in microwave and millimeter wave electronically steered,phased array antennas for a voltage controlled phase shifter. In suchsystems, the antenna beam can be steered in azimuth and/or elevation byaltering the phase of the excitation of each radiating element.

There are many known networks that can be employed for phase shiftingapplications at microwave and millimeter wave frequencies. Networks ofthe common classes have been reviewed in an article by R. V. Garverentitled "Broad Band Diode Phase Shifters", IEEE Transistors Vol. MTT20, No. 5, May 1972. These include loaded lines, hybrid coupledreflection networks, switched lines and lumped element networks (highpass/low pass). Applications exist for both digital and analog phaseshifters, the latter being favored when adaptive control of the beam issought.

The realizations of known circuits in monolithic microwave embodimentshave tended to require excessive chip area and excessive powerconsumption.

SUMMARY OF THE INVENTION

It is an object of the invention to provide an improved voltagecontrolled analog phase shifter fabricated by integrated circuittechniques for operation at microwave and millimeter wave frequencies.

It is another object of the invention to provide a novel voltagecontrolled analog phase shifter of MMIC design requiring less substratearea.

It is still another object of the invention to provide a novel voltagecontrolled analog phase shifter of MMIC design exhibiting negligiblepower consumption.

These and other objects of the invention are achieved in accordance withthe present invention in a novel analog phase shifter based on theprinciple that a shunt capacitive element in a low pass network causes aphase shift dependent upon the capacitance. A variable capacitance,therefore, produces a variable phase shift and at the same time areflection causing a standing wave and a degradation of the input VSWRof the circuit.

The degradation in VSWR is overcome in accordance with the invention, byabsorbing the shunt capacitance into an artificial transmission linenetwork with repetitive unit elements, where the shunt capacitance andseries inductance of an element are adjusted to give the requirednetwork impedance for a good input match (and specified cut-offfrequency). A cascade of these unit elements in which the shuntcapacitors are variable, gives a variable transmission phase that is thesum of the individual phase shifts of each unit element. The degradationof the input match is kept within bounds by limiting the capacitancevariation per unit element, and increasing the number of such elements.

In a practical embodiment of the invention, the artificial transmissionline is realized by a succession of serially connected microstriptransmission line-inductors and shunt connected variable capacitancediodes of value C formed on a common monolithic substrate in a MMICformat. The first and last sections of the transmission line have aninductance of value L/2 while the intermediate sections have aninductance of value L. The lines are also designed to exhibit a reactiveimpedance which is high relative to the characteristic impedance of thephase shifter at operating frequencies. All sections of transmissionline have a length substantially less than a quarter wavelength. Thevalues of L and C are chosen by a well known relationship to achieve thedesired phase shifter characteristic impedance.

The invention is best carried out with a substantial number of unitelements, for example sixteen.

DESCRIPTION OF THE DRAWINGS

The inventive and distinctive features of the invention are set forth inthe claims of the present application. The invention itself togetherwith further objects and advantages thereof may best be understood byreference to the following description and accompanying drawings inwhich:

FIGS. 1A and 1B are views of a novel voltage controlled continuouslyvariable phase shifter fabricated by monolithic microwave integratedcircuit techniques; FIG. 1A being a plan view of the entire phaseshifter consisting of sixteen individual phase shifter sections thatform an artificial transmission line; and FIG. 1B being a perspectiveview of a variable capacitance element and the connections between thecapacitance element and the inductive elements within a section of thephase shifter;

FIG. 2 is a graph illustrating the variation of gate-to-source/draincapacitance with voltage of a high electron mobility transistor (HEMT)that has its source and drain electrodes connected together, whichdevice, suitably scaled, is repeated in each section of the phaseshifter to provide the voltage responsive capacitance means to achievecontinuous phase variation, and

FIG. 3 is a simplified equivalent circuit representation of the novelphase shifter of FIG. 1, illustrating the theoretical model, which theindividual phase shifter sections approximate;

FIG. 4 is a more detailed equivalent circuit representation of the novelphase shifter of FIG. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENT

A novel continuously variable voltage controlled phase shifter inaccordance with the invention is illustrated in FIGS. 1A and 1B. Thenovel phase shifter may be fabricated using monolithic microwaveintegrated circuit techniques upon a Gallium Arsenide substrate. Whilethe phase shifter may be used at frequencies below 20 GHZ, its primaryadvantage lies in a range extending above 20 GHZ, in which it is capableof achieving the required 360° of phase shift on a substrate whosedimensions are as small as 0.018×0.060 inches for a 44 GHZ design, itbeing recognized that the dimensions may be smaller or larger as afunction of the frequency.

The novel phase shifter is designed to have a characteristic impedanceof 50 ohms and is bidirectional in that of two signal ports, either onemay become the input port with the other port becoming the output port.The illustrated embodiment operates over a 2 GHZ frequency band in thevicinity of 44 GHZ and provides a continuous analog phase shift of fromzero to 360° under a single voltage control. In a practical embodiment,the insertion loss for the phase shifter is theoretically less than 10.6db and the voltage standing wave ratio (VSWR) is less than 1.6:1. Theloss is largely dependent upon the cut-off-frequency (Fco) of thevariable capacity semi-conductor. The cut-off frequency is defined asfollows:

    Fco=1.0/2πRC                                            (1)

where R and C are the series resistance and capacitance respectively ofthe device.

The novel phase shifter may be used as a separate MMIC component in ahybrid arrangement employing larger numbers of like phase shiftercomponents or as a "cell" in a larger integrated MMIC arrangement. Auseful application of large numbers of phase shifters, is in abeamformer in a phase-steered transmit or receive array in which eachelement of the array is provided with a variable phase shifter, thephase of each phase shifter being electrically adjusted to form the beamand steer the array.

As will be explained, the novel phase shifter is realized as anartificial transmission line made up of multiple sections, connected incascade, each section consisting of an equivalent pair of seriesconnected inductances and a shunt connected variable capacitor connectedin a "tee" configuration. The equivalent inductors are made up of shortlengths of high impedance transmission line, and the variable capacitorsare two electrode semi-conductors of a design optimized to exhibit aspecified capacitance change with voltage and minimum equivalent seriesresistance. Appropriate semiconductors include diodes and field effecttransistors and high electron mobility transistors modified byconnection of the source and drain electrodes together, the controlvoltage being applied between gate and source/drain electrodes. Thecapacitance is typically the depletion capacitance and the resistance ispredominantly the undepleted semi-conductor resistance and the contactresistance. The elements of the phase shifter are disposed on theGallium Arsenide substrate illustrated in FIG. lA.

Referring now to FIG. 1A, a simplified plan view of the novel phaseshifter is shown. The elongated Gallium Arsenide substrate is shown at10 with signal ports P1 and P2 centrally disposed at either end. TheGallium Arsenide substrate is of semi-insulating material and typically0.005" in thickness. It is provided with a metallization on itsundersurface to which connections may be made by plated through holesand which may provide a common ground plane for conductors disposed onthe upper surface of the substrate thereby forming microstriptransmission lines.

The signal port to the left, using the orientations in FIG. 1A isdesignated P1 and the signal port to the right is designated P2. A firstrow of four plated through holes 11, 12, 13 and 14 is disposed adjacentto the upper edge of the substrate and extends parallel to the majordimension of the substrate. These plated through holes are elongatedparallel to the major dimension of the integrated circuit, permittingeach to provide a ground contact for two variable capacitancesemi-conductors, yet to be described. A second row of four platedthrough holes 15, 16, 17 and 18 is disposed adjacent to the lower edgeof the substrate. These plated through holes 15-18 are of the sameelongated configuration as the plated through holes 11-14, permittingeach to provide a ground contact for two variable capacitancesemi-conductor devices. The members of the upper row of plated throughholes are displaced along the major dimension of the substrate slightlyto the right of the plated through holes in the lower row. The groundcontacts are "broken-up" in order to prevent propagation of undesirableslotline modes between what would otherwise be two parallel groundconductors.

The plated through holes, whose distribution over the upper surface ofthe substrate 10 has just been described, are of a conventionalconfiguration. The under surface of the substrate is provided with acontinuous metallization and the upper surface of the semi-insulatingGallium Arsenide substrate is suitably prepared for acceptance of alayer of metallization. The plated through hole accordingly provides ametallization which contacts the under surface metallization, lines thewall of the vertical hole in the substrate material and extends over theupper surface of the substrate in the manner generally depicted by theplan view of FIG. 1B.

The variable capacitance elements of the arificial delay line areprovided by the variable capacitance semi-conductor devices or diodes D1to D16. These semi-conductor devices are two terminal devices disposedin each of the sixteen U-shaped indentations formed in the inward facingedges of the metallizations 11-18. The formation and the connection ofthe semi-conductor devices to the plated through holes and to thetransmission line elements which interconnect the capacitance elementsare best seen in FIG. 1B. In the scale of FIG. 1A these details cannotbe shown, but it should be indicated that the semi-conductor devices,being two terminal devices, each have one terminal connected to theupper surface metallization of a plated through hole and one terminalconnected to two transmission line elements so as to maintain serialcontinuity within the phase shifter.

The U-shaped indentations are disposed in two rows of eight; one row ofeight being formed in the upper row of plated through holes 11-14 andthe other row of eight being formed in the lower row of metallizations15-18 to permit equivalent connections between semi-conductor devicesalong the phase shifter. The spacing of the indentations within eachhole metallization and between adjacent hole metallizations is madeequal and the off-set between indentations on the upper row ofmetallizations is displaced by one-half the interval between adjacentindentations on the lower row of metallizations so that the lineardistances from the indentations on one row of hole metallizations to thenearest pair of indentations on the opposing pair of hole metallizationsis equal.

The semi-conductor diodes D1-D16, providing the voltage controlledcapacitance, are disposed in the indentations of the holemetallizations, the numbering sequence following from left to right andentailing locations in alternately lower and upper metallizations. Afirst electrode of each of the semi-conductor devices is electricallyconnected to the adjacent plated through hole thus providing a veryshort low inductance ground path to each variable capacitance device,and a second electrode is connected to the two transmission lineelements, acting as equivalent inductances, which cross the spacebetween rows of hole metallizations and contact the corresponding secondelectrodes of preceding and succeeding semi-conductor devices in thephase shifter.

The phase shifter is completed by a succession of narrow conductivestrips T1 to T17 which form short lengths of high impedance transmissionline commencing at the inner tip of the pad P1, continuing to thesemi-conductor diodes D1 to D17, and terminating at pad P2. In theprocess, the first transmission line segment T1, which is approximatelyone-half the length of the transmission line segments T2 to T16, isconnected between the pad P1 and the second terminal of "diode" D1. Thenext full length transmission line section T2 is connected between thesecond terminal of diode D1 and the second terminal of the diode D2.Similarly, full length transmission line segments T2 to T16 areconnected between the second terminal of the diode in one row of eightdiodes to a second terminal of a succeeding higher numbered diode in theother row of diodes. At the second terminal of the diode D16,transmission line D17, which is approximately one-half the length of thetransmission lines T2 to T16 connects the second terminal of the diodeD16 to the pad P2, completing the phase shifter.

The physical construction of a variable capacitance device and itsinterconnection with the virtual inductances is illustrated in FIG. 1B.The semi-insulating Gallium Arsenide substrate 10 is shown in theforeground with variable capacitance diode D2 being the principalsubject of the illustration. The diode D2 is formed on a Mesa formedabove the plane of the semi-insulating substrate using a constructioncommonplace to high electron mobility transistors. The Mesa includes anundoped Gallium Arsenide buffer layer 21, an undoped Aluminum GalliumArsenide spacer 22, the high electron mobility channel 23 of highlydoped n⁺ Aluminum Gallium Arsenide. The gate electrode contacts theregion 23. The next layer 24 is of highly doped n⁺ Gallium Arsenide,upon which an ohmic contact 25 corresponding the source/drain isapplied. In order to achieve optimum contact, the ohmic contact 25 isone involving Gold, Germanium, Nickel, Silver, and Gold. The electrodecorresponding to the gate may be termed the "anode" and thatcorresponding to the source/drain the "cathode", recognizing that thedevice is a rectifier favoring current flow of the appropriate polarity.

The variable capacitance diode is dimensionally quite small having acapacitance of only a few tens of femto Farads for operation atmillimeter wavelengths. The central gate electrode or anode is elongatedand representable as a finger having a width of 1/4 micron and a lengthof 30 microns, with the U-shaped source/drain or cathode extendingaround the finger. The foregoing dimensions are exemplary, and may beadjusted to increase the gate width while holding the gate area andhence, device capacitance approximately constant. This adjustment is inthe interests of increasing manufacturing yield and avoiding the needfor electronic beam lithography. Because of the Mesa construction, thecontacts to the anode and to the cathode are both elevated in relationto the semi-insulating Gallium Arsenide substrate and are optionally airor dielectric bridges. Connection is made from the anode (gate) to thesurface metallization of the microstrip transmission lines T2, T3 by afirst air bridge 26 which spans the intervening region and contacts onlythe gate and common terminus of transmission line elements T2, T3.Similarly, contact is made between the cathode of the semi-conductordevice by a second air bridge 27 which makes the connection between themetallization 11 of a plated through hole and the upper cathode(source/drain) contact 25.

One may, of course, use another form of variable capacitance diode thanthe one illustrated. For instance, the device may be fabricated usingFET compatible material. Lower losses are normally available onmaterials specifically designed for varactor diode realization. However,the advantage of a variable capacity device using HEMT or FET materialis in the ability to integrate the phase shifter with other circuitsthat employ active three-terminal transistors on a common substrate.

A phase shifter designed for 44 gHz operation, and employing sixteensections, and in which the diodes are formed on HEMT material to allowintegration with other active components, is calculated to exhibit acontinuous phase shift from zero to 360° under a voltage variationthrough zero bias of about one and one-half volts. A 0°-360° analogphase variation contemplates a 3.6:1 capacitance swing in the individualcapacitive elements.

For simplicity, the control bias circuitry has not been shown in FIG.1A, but is depicted in FIG. 3. The control circuit requires a filter toexclude signal frequencies connected between the source of control biasand the signal terminal to which it is applied. Since the transmissionlines are of low dc resistance and the currents small or negligible, oneconnection at either end or at an intermediate point on the phaseshifter is adequate. The second terminal may be the ground plane of thesubstrate.

FIG. 2 provides a graph of the variation of the gate-to-sourcecapacitance with voltage of a HEMT device. In this instance, thedimensions of the "gate" electrode are 0.25×150 micrometers. Theillustrated capacitance must be scaled down by a factor of approximately5 for the specific design. This is achieved by scaling the "gate" area.The capacitance versus voltage characteristic is non-linear, andaccordingly, may be accommodated by using a non-linear conversion of thecontrol signal or by restricting the adjustment to the more linearportion of the characteristic. The number of phase shifters may alsoincreased to achieve a larger phase shift range.

In the 44 GHz phase shifter design, the maximum required diode capacityis 0.07 pF with a 3.6:1 variation and an estimated cut-off frequency of350 GHz. (A higher cut-off frequency would be preferable, figures ashigh as 2000 GHz being attainable with other device types.) The gateelectrode is 30 microns long 0.25 microns in width, connected to thetransmission line elements. In the same example, the length of the fulllength transmission line elements (T2-T16) is 185 microns with a widthof 14 microns. The half length transmission line elements (T1 and T17)are 92.3 microns in length and also of 14 microns width.

An understanding of the design is best approached by use of thesimplified equivalent circuit representation of FIG. 3. In FIG. 3, thephase shifter may be regarded as an artificial transmission lineconsisting of sixteen tee sections connected between the input pads P1and P2. The drawing illustrates the first two and last of the sixteentee sections. Each tee section consists of a pair of serially connectedinductive elements of value L/2 and a variable capacitor of value Chaving one terminal connected to the node common to the two inductiveelements and the other terminal connected to ground.

In the realization of the equivalent circuit of FIG. 3, the serialinductances are realized by short lengths of high impedance transmissionline. More particularly, the first serial inductance of value L/2 isrealized by a short length of transmission line T1 and the capacitor Crealized by the diode D1. The second serial inductance of value L/2 inthe first section and the first serial inductance of value L/2 in thesecond section are realized by the transmission line T2 extendingbetween diodes D1 and D2. As one proceeds along the real phase shifter,each real transmission line element T2 to T16 represents two successiveinductances of value L/2, the first a member of a prior tee section andthe second a member of the following tee section. The final transmissionline T17 has a length equal to approximately half that of thetransmission lines T2 to T16. Transmission line T17 connects diode D16to the pad P2 and has an inductance of the value L/2.

The phase shifter is designed to match the input impedance to which thephase shifter is connected. The characteristic impedance (Zo) of thephase shifter may be approximated as follows:

    Zo=(L/C-w.sup.2 L.sup.2 /4).sup.1/2

where w=angular frequency=2πf.

This initial value for the characteristic impedance is based on idealcircumstances including "lumped" inductances which ignore suchparasitics as the self inductance of the plated through hole groundconnections and neglects the series and shunt resistance of realsemi-conductor devices.

The simplified expression is useful as an aid to understanding thedesign. If the value of L and C are selected for an exact input match ata specified frequency, no reflection and no phase shift will occur. If,however, a phase shift is sought, and this is achieved by varying thecapacitance of the shunt device, the match will no longer be exact andboth a reflection and a phase shift will occur, proportionate to theimpedance mismatch.

Should the phase shifter consist of only a single tee section, a largephase shift, achieved by a large adjustment in the value of thecapacitor in a single section filter, would provide a very largemismatch and be intolerable. If, however, a large number (e.g. 16) ofelemental sections are cascaded, with each elemental section requiredonly to produce a small fraction of the total phase shift (e.g. 1/16),then the mismatch may be relatively small. The input VSWR degradationmay be kept within acceptable bounds defined by the capacitancevariation. Using more elements reduces the required capacitance swingper element and hence improves the achievable VSWR. More elementshowever produce more insertion loss forcing a compromise between minimumVSWR and maximum tolerable loss. The calculated worst case VSWR for the44 GHz design is less than 1.6:1.

Should the individual diodes be perfect diodes without loss, one couldreadily increase the number of sections without limit. Practical upperlimits with available diodes could be higher than 16. In these cases,use of this higher number of sections would reduce the capacitance swingrequired of each device, and reduce the VSWR proportionately.

The selection of sixteen phase shifter sections in the exemplary 44 GHzdesign is set by the loss (e.g. 10.6 db) which can be tolerated. Thisloss is produced using semi-conductors of the type herein describedcompatible with Gallium Arsenide HEMT or FET processing. Sixteen filtersections, which produce 10.6 db of loss, represents a practicalcompromise for diodes of this "quality". The figure of merit for thediode is the Fco (i.e. the cut-off frequency). While the indicateddesign goals can be met at 44 GHz, with diodes having a cut-offfrequency of 350 GHz, a much reduced loss would result with diodes withhigher cut-off frequencies (e.g. 1000-2000 GHz). A semi-conductorcompatible with the desired processing but further optimized for thevariable capacitance role, would reduce losses significantly.

The indicated hardware dimensions are derived from a more exact model ofthe phase shifter than that of FIG. 3. The more exact model, which takesinto account the parasitic elements, is illustrated in FIG. 4. Theillustrated hardware design benefits from the more complex model and isalso further optimized with the aid of circuit analysis and withoptimization software which examines the several conflicting trade offsrequired to meet a comprehensive specification.

As illustrated in the more detailed equivalent circuit of FIG. 4(showing only the first three sections), the transmission line is bestrepresented by a pi network including a pair of shunt capacitances ateither end of a series inductance. The series inductance is that whichis specifically utilized while the shunt capacitances are disregarded inthe simplified model. In the more accurate model of FIG. 4, however,these capacitances ct coincide with the placement of the variablecapacitance semi-conductor devices. These semi-conductor devices areaccordingly, made smaller to absorb the capacitance already presented bythe transmission line realization The semi-conductor devices aremodelled as series RLC elements to account for diode resistance Rd,diode capacitance Cd and plated through hole inductance Lvia (0.015 nH).

The foregoing computer analysis indicates a maximum insertion loss of10.6 db with a 6.0 db slope. The computed impedance match is typically20 db with a 13 db worst-case value corresponding to a VSWR of <1.6:1.The computed phase versus frequency characteristics show that thestructure has a constant time delay and exhibits an increasingphase-shift with frequency.

The term "artificial transmission line" has been used to denote thepresent phase shifting structure. The term is intended to mean atransmission line formed of discrete lumped elements, as opposed to a"continuous transmission line" represented by a coaxial line, strip-lineor a wave guide. The term "artificial transmission line" is also notintended to include a periodically loaded continuous transmission line.While the present phase shifting structure uses sections of transmissionline, each section is short, substantially less than a quarterwavelength, and therefore properly regarded as a "lumped" inductanceelement, or more precisely as a lumped inductance accompanied by twoshunt capacitors in a "pi" network. The diodes appear as variablecapacitors primarily, and while having serial parasitic resistance andinductance are also lumped components. At frequencies where the devicedimensions are an appreciable fraction of a wavelength, the lumpedmodels of the individual components would be better modelled as"distributed" networks, but the design concept remains unchanged. Theadvantage of the use of a short transmission line section as a lumpedinductance element is in the reduction in size of a multi-unit elementphase shifter. In a traditional periodically loaded continuoustransmission line, the intervals between loads for minimum reflectionare at one quarter wavelength intervals to insure that destructivecancellation of reflections occur. The present lumped artificial lineavoids the spacial requirement of that design concept. In the example,the length of individual transmission line inductors and therefore thesize of the complete phase shifter, may be reduced using the inventiveprinciples, by a factor of three or four.

A major advantage of the artificial transmission line design istherefore its compactness. A sixteen section filter may be fabricated inan area of 0.060" by 0.018" for operation at 44 GHZ. This size issufficiently small to permit use of relatively large numbers of suchphase shifters on a common chip shared with additional electroniccircuitry.

A second advantage of the circuit, which is its low power consumption,is best realized using conventional (e.g. Schottky) diodes in preferenceto HEMT or FET devices with source and drain interconnected. A diodeusing HEMT or FET geometry optimized for gain devices, when forwardbiased to achieve the desired range of capacitance variation, may drawcurrent but the current is often not large enough to be of concern.Conventional diodes which exhibit the desired capacitance changes withbias voltage may remain reversely biased through the adjustment rangeand thus may never enter forward conduction. In the first case, thecurrent drain is quite small compared to competitive designs and in thesecond case, the current drain, which consists of diode leakage currentonly, is negligible.

What is claimed is:
 1. A monolithic microwave integrated circuit (MMIC)voltage controlled, analog phase shifter having a specifiedcharacteristic impedance (Zo) and specified worst case VSWR andrequiring minimum substrate area at millimeter and microwavewavelengths; comprising:(A) a substrate of semi-insulating GalliumArsenide having a ground plane on the under surface thereof, (B) a firstinput-output port, (C) a second input-output port, (D) an artificialtransmission line comprising(1) an (n+1) fold succession of sections ofmicrostrip transmission line, where n is an integer, consisting of saidground plane and a conductor formed on the upper surface of saidsubstrate, the sections having a high impedance relative to saidcharacteristic impedance Zo and being serially connected between saidfirst and second input-output ports, the first and last sections havingan inductance value of L/2 and the intermediate sections having aninductance value of L, all sections of transmission line having a lengthsubstantially shorter than one-quarter wavelength; (2) an n foldplurality of semi-conductor elements having at least a first and secondterminal, each semi-conductor element having a variable capacitance ofthe value C, the capacitance thereof being a function of an appliedvoltage, the first terminal of each semi-conductor element beingconnected to a respective connection between transmission line sectionsand the second terminal coupled to substrate ground through a platedthrough hole, said semi-conductor elements being arranged along a firstline in a sequence of odd numbered semi-conductor elements, and arrangedalong a second line in a sequence of even numbered semi-conductorelements, the second line being displaced from the first line andparallel thereto, the intermediate members of said (n+1) fold successionof transmission line sections extending between said succession of oddand even numbered semi-conductor elements in said first and secondlines, and said plated through holes being arranged in a second pair ofparallel lines, outside of and close to said two lines of semi-conductorelements to permit direct paths without cross-overs for eachtransmission line section between consecutive first terminals of saidsemi-conductor element and short connections between the second terminalof each semi-conductor element and ground, the semi-conductor elementsin one line being staggered in relation to the semi-conductor elementsin the other line to provide equal spacing and thereby equal lengthtransmission sections between the first terminals of said semi-conductorelements, the values of L and C being chosen to achieve the desiredcharacteristic impedance in approximate satisfaction of the expression

    Zo=(L/C-w.sup.2 L.sup.2 /4).sup.1/2

where w=the angular frequency 2 pi f neglecting transmission line andsemi-conductor element parasitics, and (E) means for applying a controlvoltage between the first and second terminals of each variablecapacitance semi-conductor element to achieve the desired phase shift.2. The phase shifter set forth in claim 1 wherein said semi-conductorelements are field effect transistors, each having source, drain andgate electrodes, said source and drain electrodes being connected tosaid second terminal of the element, and said gate electrode beingconnected to said first terminal of the element.
 3. The phase shifterset forth in claim 1 wherein said semi-conductor elements are highelectron mobility transistors each having source, drain and gateelectrodes, said source and drain electrodes being connected to saidsecond terminal of the element, and said gate electrode being connectedto said first terminal of the element.
 4. The phase shifter set forth inclaim 1 whereinsaid plurality of plated through holes is approximatelyn/2 in number, the semi-conductor elements in one line being connectedin pairs to individual plated through holes and the semi-conductorelements in the other line are connected in pairs to individual platedthrough holes, so that the succession of plated surfaces on saidsubstrate is interrupted to prevent an undesired stripline mode.
 5. Thephase shifter set forth in claim 1 wherein said semi-conductor elementsare Schottky diodes.
 6. The phase shifters set forth in claim 1 whereinsaid semi-conductor elements are varactor diodes.